“Critical mode/interleaved PFC IC R2A20112 capable of forming low-noise anti-harmonic power supply of 1.5 kW” by Mamoru Kitamura, in the May 2008 issue of Transistor Technology, pp. 176-184, published by CQ Publishing Co., Ltd. in August, 2008 discloses a power factor correction circuit. The power factor correction circuit includes a master power factor correction circuit and a slave power factor correction circuit. The master and slave power factor correction circuits are connected to the same DC power supply, and are connected in parallel to each other. The master and slave power factor correction circuits have the same structure.
The master and slave power factor correction circuits are what are called booster chopper circuits, and each include a reactor, a diode, and a switching element. A MOS field-effect transistor is used as this switching element.
The switching element of the slave power factor correction circuit is brought into conduction when a predetermined period has elapsed after the switching element of the master power factor correction circuit is brought into conduction. So, these power factor correction circuits operate in what is called an interleaved manner.
Japanese Patent Application Laid-Open No. 2008-193818 and Japanese Patent Application Laid-Open No. 2007-252177 disclose techniques relating to the present invention.